An operational amplifier, often written as Op Amp, can be configured to perform different tasks depending on the application. Referring to FIG. 1, one of these configurations is as a difference amplifier 10, wherein a feedback resistor, denoted R2 is provided from the output of an Op Amp 20 to the inverting input of Op Amp 20. A second resistor R2, typically of the same value as feedback resistor R2, is provided between the non-inverting input of Op Amp 20 and a common potential, illustrated without limitation as ground. Additionally, a matched pair of resistors R1 are provided, a first end of each of which are coupled respectively to the inverting, and non-inverting inputs of Op Amp 20. The second end of each resistor R1 provides a lead, denoted respectively INPUT1, INPUT2, for connection to a first end of each of the two signal sources, denoted respectively VS1 and VS2, and a second end of each of the two signal sources are connected to the common potential. For clarity, the internal source resistance of the each of the two signal sources are illustrated, denoted respectively RS1 and RS2.
The output of Op Amp 20, representing the output of difference amplifier 10 and denoted VO, neglecting internal source resistances RS1 and RS2, is determined as:VO=R2/R1*(VS2−VS1)  EQ. 1The input resistance, RIN, of difference amplifier 10, is determined as:RIN=2*R1  EQ. 2In the presence of finite internal source resistance RS1 and RS2, VO is determined as:VO=(−R2*VS1)/(R1+RS1)+VS2*(1+(R2/R1+RS2))/(1+(R1+RS2)/R2)  EQ. 3In the event that R1>>RS1 and R2>>RS2 then EQ. 3 simplifies to EQ. 1.
The above classic difference amplifier configuration has advantages and disadvantages. The biggest advantage is the simplicity of the design, but one of the disadvantages is that the sources driving the inputs need to have very low source resistance, in order for EQ. 3 to simplify to EQ. 1. Unfortunately, this is not always practical.
In the absence of sources driving the input with very low source resistance, the prior art further suggests the use of input buffers to eliminate the effect of source resistances RS1, RS2 from the operation of difference amplifier 10. Preferably the input buffers provide high input resistance towards signal sources VS1, VS2 so as not to load the respective signal sources, and low output resistance to that EQ. 3 will reduce to EQ. 1.
FIG. 2 illustrates such an embodiment, where buffers 30 are provided between respective signal sources VS1, VS2 and input leads INPUT1, INPUT2, respectively of difference amplifier 10. Each buffer 30 is illustrated, without limitation, as a source follower circuit, comprising a current source, denoted ID, and a transistor, illustrated without limitation as an NMOSFET. For clarity, the transistor of buffer 30 connected to signal source VS1 is denoted M1, and the transistor of buffer 30 connected to signal source VS2 is denoted M2. In greater detail, the output of signal source VS1, illustrated for simplicity with source resistance RS1 in series with the positive output thereof, is connected to the gate of transistor M1. The drain of transistor M1 is connected to the common potential, illustrated without limitation as ground, and the source of transistor M1 is connected to the output of the respective current source ID and to input lead INPUT1 of difference amplifier 10, which is in all respects identical to difference amplifier 10 of FIG. 1. The output of signal source VS2, illustrated for simplicity with source resistance RS2 in series with the positive output thereof, is connected to the gate of transistor M2. The drain of transistor M2 is connected to the common potential, illustrated without limitation as ground, and the source of transistor M2 is connected to the output of the respective current source ID and to input lead INPUT2 of difference amplifier 10. The inputs of the respective current sources ID are connected to a voltage potential.
Use of a source follower circuit for buffer 30, as described above, provides simplicity and low cost, however it presents certain difficulties. In particular, the current through the respective transistors M1, M2 of buffers 30 is determined by:IM=(k′/2)*(W/L)*(VGS−Vt)2  EQ. 4where k′ and Vt are constants of the respective transistors M1, M2; W is the width of the respective transistors M1, M2; L is the length of the respective transistors M1, M2; VGS represents the potential between the gate and source of the respective transistors M1, M2; and Vt is the threshold voltage of the respective transistors M1, M2. As described above in relation to EQ. 2, differentially, the input resistance to difference amplifier 10 is 2*R1. A difference in output voltage between signal source VS1 and signal source VS2, translated into a voltage difference between INPUT1 and INPUT2, will result in a differential between the current passing through M1, denoted particularly as current IM1, and the current passing through M2, denoted particularly as current IM2. In greater detail:IM1−IM2=(INPUT1−INPUT2)/(2*R1)  EQ. 5As indicated by EQ. 4, such a difference in current can only be manifested as a difference in VGS between M1 and M2, resulting in a systematic offset into the input of difference amplifier 10 as the difference between the source voltages of transistors M1 and M2 no longer represent solely the difference between the gate voltages of transistors M1 and M2, i.e. the difference between the source voltages of transistors M1 and M2 no longer represent solely the difference between signal source VS1 and signal source VS2.
Unfortunately, the prior art does not supply a difference amplifier arrangement which exhibits high input impedance without introducing any undesired offsets.